ENGINEERING & SOURCING GUIDES
PCB Controlled Impedance Tolerance Selection
Select controlled impedance tolerance from the channel’s demonstrated electrical margin and the fabricator’s ability to hold and measure the approved construction. Start with the exact interface and device requirements, then test proposed manufacturing limits in the channel model. A familiar percentage on a quotation does not establish that the finished link will pass. A tighter percentage is useful when it protects a requirement that matters.
This guide concerns choosing the permitted impedance range. It does not supply universal targets for USB, PCIe, memory or RF traces. Use the stack-up approval guide to document the physical construction after the electrical owner selects the requirements.
Separate three different limits
The interface’s channel requirement, the designer’s nominal trace impedance and the bare-board acceptance range are related but different. A channel can contain package escape traces, vias, connectors, board traces and cables. A fabrication coupon represents a defined trace construction. Its result cannot certify all those discontinuities.
Texas Instruments’ Jacinto7 interface guidance, revision A ties impedance and tolerance to the protocol and explains the influence of geometry, dielectric properties and adjacent layers. Its device list and interface sections establish application context. Do not apply an introductory example to every differential pair on another product.
TI’s High-Speed Interface Layout Guidelines, revision J also contains different device/interface limits in its tables. This is a reason to identify the applicable row, not permission to select whichever row is easiest for procurement. Record the controlling documents, operating mode and approved exceptions for each net class.
If the system owner sets a stricter channel budget than the component reference design, retain that decision. Disagreement between requirements should remain an engineering query until the responsible owner resolves it. A supplier should not have to infer which document takes precedence.
Allocate margin to the complete channel
Start with the released topology: driver and receiver models, package connections, trace lengths, vias, connectors and termination. Sweep the proposed impedance range together with relevant loss, skew and device corners. A nominal trace-only model can conceal an unfavorable connector transition or combination of manufacturing changes.
Choose the pass criterion before comparing tolerances. Depending on the interface, it may include eye margin, timing, return loss or another specified metric. Preserve the model version and evaluation locations. A statement that “simulation passes” leaves the next engineer unable to distinguish a complete channel from an ideal transmission line.
First estimate sensitivity to identify which construction deserves attention; then validate the actual supplier proposal before release. If changing the dielectric thickness requires a different trace width, model both changes. It is no longer a pure tolerance adjustment. Include the actual permitted geometry rather than assuming the original drawing still describes the proposed board.
| Input | Decision supported | Record to retain |
|---|---|---|
| Interface and device limits | Required link behavior | Document revisions, operating mode and exceptions. |
| Channel sensitivity sweep | Range that preserves margin | Topology, corners, metrics and worst-case results. |
| Fabrication construction | Geometry that can be produced | Pressed dielectric, copper, width, pair gap and material. |
| Measurement definition | Quantity evaluated against the drawing | Coupon structure, mode, evaluation region and reporting method. |
| Exception process | Authority to disposition a deviation | Decision role and written approval tied to the revision. |
Illustrative example: percentage versus channel margin
Illustrative example only: a hypothetical 100 Ω differential target with ±10% tolerance permits 90–110 Ω. A ±5% tolerance permits 95–105 Ω. These figures explain arithmetic; they are not recommended limits for an interface. Removing 5 Ω at each end does not produce a fixed percentage improvement in eye opening.
Suppose both ranges pass for a short board link, while a longer variant becomes marginal at one combined corner. Locate the sensitivity before changing the order. The response might be tighter trace control, a different construction, a connector change or a shorter route. Applying the tighter percentage everywhere could leave the actual problem unchanged.
If a model passes only at nominal geometry, neither range has been justified. If the tighter range is essential but the proposed process cannot demonstrate it, the drawing and quotation conflict. Resolve the construction or topology before release. A successful prototype at one measured value is not evidence that every permitted corner is acceptable.
Write a testable fabrication note
Name the signal layer, reference layers, measurement mode, nominal value and allowed range. Include trace width and pair spacing in the approved stack-up. State whether the supplier may adjust geometry to achieve impedance, and which adjustments require approval. Permitted changes must also respect breakout, spacing and length constraints.
Ask how the coupon represents the board. Identify the controlled structures and how the results connect to delivered panels or lots. Several geometries on one layer may require distinct structure identifiers. A report containing only numerical results without coupon identities can be impossible to reconcile with the drawing.
Agree measurement settings and evaluation regions with the supplier. Launch artifacts, line ends and a stable trace region answer different questions. Have the electrical and test owners confirm a method suited to the structure; do not invent blanket instrument settings in the purchase order. Define treatment of uncertainty and borderline results before they occur.
The multilayer PCB requirements provide the manufacturing context. Use the quality evidence guide to organize reports. Coupon acceptance accompanies system validation; it does not replace it. A passing trace coupon cannot clear an unmodeled connector escape.
Release and change-control checklist
- Identify each controlled net class and the exact applicable electrical requirement.
- Confirm the tolerance sweep used the released topology and relevant operating corners.
- Approve material, dielectric thickness, copper and geometry as one construction.
- Resolve supplier exceptions and permitted adjustments in writing.
- Define coupons, measurement mode, report identifiers and acceptance handling.
- Repeat relevant analysis after a material, stack-up, launch or routing change.
Retain a short decision note explaining why the selected tolerance is sufficient. It helps procurement distinguish a meaningful requirement from a copied drawing default during reorders and second-source reviews. Keep both the accepted range and the assumptions that justified it; either can become invalid when the channel changes.
Send the impedance decision with the files
For a quotation from PCB Manufacturer in China, include the board revision, stack-up, controlled net classes, nominal values, tolerances, permitted geometry adjustments and requested coupon records. Identify any channel-sensitive structure that remains under engineering review.